| 摘要 |
PURPOSE:To process many interruption requests of the same level at high speed by dividing the same interruption level into plural interruption signal lines and processing the interruption discriminating processing of many input/output controllers connected to the same interruption level at each interruption signal line. CONSTITUTION:A CPU 1 outputs an address line ADR to input/output controllers IOC2-4, The IOC 2 connects an interruption signal line INTx0 of an interruption level x0 and the IOCs 3, 4 connect the INTx1 of the same interruption level x1 to an interruption expansion control circuit INTC 10. ADR and DATA lines are connected to the INTC 10 to apply similar selection control to the IOC. The INTx0, x1 give inputs to an OR gate 11 and bus drivers 12-14, the result is an output INTx of the gate 11, which is given to the CPU 1. When the CPU 1 inputs the interruption request of the INTx, the INTC 10 is accessed and the interruption of the INTx0, x1 is read from the DATA line. When the interruption request from the INTx0 exists, the IOC 2 is accessed and when the interruption request from the INTx1 exists, the IOCs 3, 4 are accessed to discriminate which IOC is interrupted.
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