| 摘要 |
PURPOSE:To improve the detection performance by using two RS FFs, an inverter, an AND gate and a D FF so as to operate the title circuit at both from low to high level and from high to low level changes with less number of components. CONSTITUTION:A signal inputted to a pulse input terminal 1 is inputted to a set terminal S of a RS-FF circuit 7 and also inputted to a set terminal S of a RS-FF circuit 8 via an inverter 9. Outputs of output terminals Q of both the RS-FF circuits 7, 8 are ANDed by the AND gate 10 and the result is inputted to a data terminal D of the D-FF circuit 1. A clock impressed to a clock input terminal 3 is inputted to a reset terminal R of both the RS-FF circuits 7, 8 and a clock terminal C of the D-FF circuit 11. Then a signal at an inverting output terminal Q' of the D-FF circuit 11 is sent to a pulse interruption output terminal 6.
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