发明名称 |
High speed clocked, latched, and bootstrapped buffer |
摘要 |
From an input signal, a buffer circuit derives an output signal which changes in logic state in synchronism with the rising edges of a first clock and whose value follows the input signal but in opposite logic state. The first clock directly drives the buffer output through a first transistor whose gate is controlled by the output of a NOR-gate. The buffer output is connected to ground through two FET's whose gates are controlled respectively by the first clock and the input signal as sampled by a second clock. The buffer output after being delayed and the input signal as sampled by the second clock are applied to the inputs of the NOR-gate. By adding an FET between the gate of the first transistor and the output of the NOR-gate the bootstrap action caused by the gate-drain parasitic capacitance of the first transistor reduces the delay between the rise of the buffer output and the rising edge of the first clock. A holding circuit may be used to hold the value of the buffer output despite changes in the states of the clocks.
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申请公布号 |
US4617476(A) |
申请公布日期 |
1986.10.14 |
申请号 |
US19840661345 |
申请日期 |
1984.10.16 |
申请人 |
ZILOG, INC. |
发明人 |
DALRYMPLE, MONTE J. |
分类号 |
H03K19/017;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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