发明名称 CERAMIC PACKAGE FOR SEMICONDUCTOR ELEMENT
摘要 PURPOSE:To enable an electronic circuit to perform calculation or other processing at an increased speed, by utilizing silver or copper, or an alloy there of for multilayer interconnection layers, while utilizing alumina having a high purity of 90% or more as an insulator material, and forming the multilayer interconnection layer by pressing the liquid metal. CONSTITUTION:A wiring layer 10 is provided by pressing a high-temperature liquid metal such as silver, copper or an alloy thereof into cavities which have been formed corresponding to the configurations as predetermined for the wiring layer 10. Accordingly, it is effectively prevented from producing pores or cavities. When a potential at an output terminal 5 of a large scale integrated circuit (LSI) 4 is changed, the potential change is transmitted through the wiring layer 10 to an input terminal 6 of an LSI 4'. The data provided by the LSI 4 is quickly calculated by the LSI 4', and the data resulting from the calculation is returned to the LSI 4 from the LSI 4'. Alumina having a high purity of 90% or more is utilized as an insulator material 1. According to this construction, the speed of the calculation or other processing of the semiconductor element can be increased.
申请公布号 JPS61230343(A) 申请公布日期 1986.10.14
申请号 JP19850071218 申请日期 1985.04.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SAKAEDA MASATAKA;ISHIDA TORU
分类号 H01L25/18;H01L23/08;H01L23/12;H01L23/538;H01L25/04 主分类号 H01L25/18
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