| 摘要 |
An aligner (FIG. 1), which has seven registers SRGA to SRGG each of 64 bits in length, is used to align incoming line signals to exchange data rate and to convert exchange rate data signals into line rate data signals. The aligner behaves as a variable delay and is required to operate in any one of three modes; (i) frame aligning 2,048 k Bits/second line signals to a 2,048 k Bits/second exchange rate, (ii) aligning 1,544 k Bits/second line signal to a 2,048 k Bits/second exchange rate and (iii) converting a 2,048 k Bits/second exchange rate to a 1,544 k Bits/second line rate. In the third mode of operation it is necessary to derive the line clock from the exchange local clock. This is achieved by forming a phase-locked loop (FIG. 5) incorporating the delay of a standard aligner and driving the loop with the exchange frame reset signal (f IN).
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