发明名称 PRECEDING '1' DETECTING CIRCUIT
摘要 PURPOSE:To obtain a preceding '1' detecting circuit which can detect the '1' nearest to the highest-order bit including the highest-order bit or the '1' nearest to the lowest-order bit including the lowest-order bit at a high speed. CONSTITUTION:When a basic clock phi becomes '0' and a preceding '1' detecting signal F from the highest-order bit becomes active '1', the output of a two-input AND circuit 9 becomes '1' and a transistor 8 is turned on. Then a zero transmitting signal line T16 to a logical block A15 is set at '0' and a transistor 3 is also turned on and, if input data D15 are '1', the output of an inverter 4 becomes '0' and '1' is outputted as the output S15 of the logical block A15. On the other hand, when the input data D15 are '0', the output of the inverter 4 becomes '1' and a transistor 5 is turned on, and then, the '0' of the zero transmitting signal line T16 is transmitted to the zero transmitting signal line T15 to the next logical block A14.
申请公布号 JPS61229121(A) 申请公布日期 1986.10.13
申请号 JP19850070234 申请日期 1985.04.03
申请人 NEC CORP 发明人 NOHARA SAYOKO
分类号 G06F7/00;G06F7/74 主分类号 G06F7/00
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