| 摘要 |
<p>PURPOSE:To reduce the number of terminals of memory and to scale down an IC package by dividing the 1st address space into at least two end address spaces and mixing them so as to access the 1st address space. CONSTITUTION:When a row address strobe signal 11 is supplied to an internal timing generating circuit 4 from an external terminal, a row address latch signal 14 is supplied to a row address buffer circuit 2, and a row side address to which an address signal 10 is supplied is latched. Simultaneously a row address latch signal 14 is supplied to a memory array 1. Then, when a column address strobe signal 12 is supplied to the internal timing generating circuit 4, a column address latch signal 15 is generated and supplied to a column address buffer circuit 3 to latch a column side address to which the address signal 10 is supplied. Simultaneously said signal 15 is supplied to the memory array 1. Afterward, an output enable signal 13 latches data in the memory array 1 to an output data buffer circuit 5, and the data is outputted as an output data DO 17 to the external terminal.</p> |
