| 摘要 |
PURPOSE:To shorten a cycle time by constituting a read data latch circuit and a selecting means with a static circuit. CONSTITUTION:Due to the activation of a row address strobe signal RAS and a column address strobe signal CAS data totaling four bits are simultaneously read out of respective blocks M0-M3 of a memory array 1, and fetched into read data latch circuits RDL0-RDL3 composed of the static circuit through I/O common data lines I00--I03. With the activation of an I/O enable signal IOE selecting signals specified by address signals Ai and Aj are sequentially activated one by one to turn on sequentially MOS transistors Q, and data held in the latch circuits RDL0-RDL3 are passed through a pair of output data lines D0B/-D0B and impressed to a data output buffer 6. Simultaneously a gate signal OE from a control circuit 5 is activated, and a read data signal is outputted.
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