| 摘要 |
PURPOSE:To share a single bus with a simple constitution by controlling the bus with the single instruction timing when the 1st microprocessor works separately and then with the time division instruction timing when both the 1st and 2nd microprocessors work together. CONSTITUTION:The 1st microprocessor 1 is connected to a bus via registers 7-10 and a gate for control of the bus. In case the 2nd microprocessor 2 is not workable, no signal is delivered from a workable signal generator 12. Thus the bus is connected to the processor 1, and the bus can be used with the single instruction timing of the processor 1. When the processor 2 is workable, the generator 12 is set at '1' and a time division signal generator 13 also starts its working. Thus the information on the addresses controlled by both processors 1 and 2 are put alternately on an address bus 3. Furthermore the control sources are changed in time division for both a data bus 4 and a write control line 5. A timing line 6 uses the signal of a write timing generator 14 of the processor 2. |
