Control loop for deflecting cathode rays in display devices

摘要

A circuit arrangement for synchronising a sequence of horizontal deflection current pulses of a cathode ray display with a sequence of synchronisation pulses contains an adjustable delay circuit which, in turn, is triggered by a synchronisation signal and triggers the generation of the deflection current pulse after a predetermined time delay. The delay is automatically controlled by a feedback loop in which the existing delay is measured by means of an RS flip flop, which outputs output pulses, the duration of which is equal to the delay. An integrator forms the mean value of the pulse chain coming from the flip flop and logically combines a reference signal with the mean value in order to generate by this means a control signal for the delay. The circuit arrangement operate with minimum bandwidth and dynamic characteristics which are free of acquisition restrictions in order to produce by this means minimum sensitivity to interference.