| 摘要 |
<p>An integrated circuit comprises a pass transistor (M40) connected to the input of a complementary inverter pair. Means (403) are included to supply to the complementary inverter a reduced voltage, as compared to the signal voltage supplied to the gate of the pass transistor. In this manner, the switching threshold of the inverter is reduced, allowing a single conductivity type of pass transistor to be advantageously used. In one embodiment, the reduced voltage is obtained by a diode-connected enhancement type field effect transistor, producing a threshold voltage drop. In another embodiment, means for supplying three power supply voltages are utilized. A delay stage for a shift register can advantageously be implemented by the present technique. Transmission gate logic circuits can also be implemented by the present technique.</p> |
