| 摘要 |
<p>A clock signal circuit receives first and second clock signals (CLOCK 0, CLOCK 1) the pulses of which are non-overlapping with respect to each other. The first and second clock signals (CLOCK 0, CLOCK 1) are applied to the source-drain paths of respective first and second MOS transistors (36, 40), the gate electrodes of which are coupled via the source-drain paths of third and fourth MOS transistors (34, 38) to the outputs of respective first and second NOR gates (31, 32) receiving the second and first clock signals, respectively, and also receiving first and second control signals. The outputs of the NOR gates (31, 32) are further connected to a third NOR gate (42) having an output connected to the gate electrode of a fifth MOS transistor (44) connected to an output line. In operation, selected, booted clock signals are supplied to the output line.</p> |
