| 摘要 |
PURPOSE:To prevent phase error generated by a slice level change or the like in binary processing from giving an influence to a bit synchronous clock produced in a PLL circuit by providing a data slice circuit, a phase synchronous loop circuit, a phase error detecting circuit, a correcting circuit and a synchronization circuit. CONSTITUTION:A binary digital signal DRF in a data slice circuit 13 is supplied to a PLL circuit 21 and a correcting circuit 22 and through an inverter 23 to an error detecting circuit 24. The error detecting circuit 24 detects phase error between the binary signal DRF and a digital signal DOUT from the PLL circuit by the other edge phase of the binary signal DRF not used in the PLL circuit, and detects error of the slice level thereby and the detected error amount is supplied to the correcting circuit 22. The correcting circuit 24, based on the error amount detected by the correcting circuit 24, corrects a recorded input digital signal DRF by a time base, thereby the data signal DOUT is read. The data signal DOUT read by the correcting circuit 22 is supplied to a synchronization circuit 25. |
