| 摘要 |
<p>PURPOSE:To ensure the stability of clock selection to noise by inverting the switching state of a selection circuit only when it is detected that a reception frame signal is incoming consecutively for a prescribed number of times within a hysteresis width provided before and after a reference value in excess of the reference value from a smaller delay time direction or a 1 larger direction. CONSTITUTION:An identification circuit 105 is provided with the 1st detection circuit 106 detecting that a received frame bit is incoming for a prescribed number of times continuously in a hysteresis width provided before and after the reference value in excess of the reference value from a smaller delay time direction and a larger direction, and the 2nd detection circuit 107, and the changeover of a reproduced clock and a fixed phase clock by a selection circuit 103 is performed only when it is detected that the received frame signal is incoming continuously for a prescribed number of times within the hysteresis width in the other state in excess of the reference value from one state. Thus, instable operation of the selection circuit 103 due to noise or jitter is prevented.</p> |
