| 摘要 |
A CMOS limiter with input hysteresis, responsive to an input signal of varying amplitude, produces an output signal which changes between at least first and second levels, the transitions occurring when the absolute value of the amplitude of the input signal exceeds predetermined reference level. The limiter is fabricated on a single integrated circuit using CMOS switched capacitor techniques. An SC switching array selects between sampled input signal and an inverted sampled input signal depending upon the value of the output signal produced by the limiter. A comparing network (comprising an active CMOS comparator responsive to a difference signal produced at a summing node) changes the level of the output signal of the limiter when the selected signal exceeds a predetermined reference value. The summing node includes a signal level storing device (i.e. a precision capacitor) for storing the reference level during the period in which the input signal is sampled. The input offset voltage of the comparator is subtracted from the selected signal to reduce the output error of the comparator due to non-zero input offset voltage. The limiter includes a clock signal generator and sequential logic responsive to the clock signal generator for synchronizing the switching of the various switched capacitor switching elements in order to provide hysteresis.
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