| 摘要 |
PURPOSE:To attain high speed operation and to reduce the number of elements by providing the 1st logic circuit forming the input signal of the 1st bit to a flip-flop (FF) and the 2nd logic circuit forming the input signal of a host bit. CONSTITUTION:The Q output signal of a D type FF 51 and an up-down signal U/D are fed to a logic circuit 55 to generate an input signal to a JK FF 52, a signal on the way of the circuit 55 and a Q' output signal from the FF 52 are fed to a logic circuit 56 to generate an input signal to a JK FF 53. A signal on the way of the circuit 56 and the Q output signal of the FF 53 are fed to a logic circuit 57 to generate an input signal to a JK FF 54. The counter acts like an up-counter by bringing the level of the mode switching signal U/D to 1 level. The signal U/D at both the modes passes through one NOR gate or one NAND gate respectively in each logic circuit. Then the number of elements is less and high speed operation is attained.
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