| 摘要 |
PURPOSE:To prevent miscounting, by arranging a gate circuit so that a logical computation is performed between output signals of first and second differentiation circuits and A-phase and B-phase pulses to generate pulses for respective countings at the rise and fall of the A phase and B phase pulses. CONSTITUTION:A logical computation is performed between output signals of first and second differentiation circuits 20 and 21 and A phase and B phase pulses. At the times t1, t3, t5 and t7, output signals alone of AND gates 34, 37, 35 and 36 will be '1' signals by logical computations with respective gates. On the other hand, at the times t2, t4, t6 and t8, all of output signals of the AND gates 30-37 will be '0' signals. In other words, at the times t1, t3, t5 and t7, signals Sa4, Sb3, Sa3 and Sb4 are outputted through the gates 34, 37, 35 and 36 and an OR gate 41 and in this case, the pulse signal outputted from the gate 41 turns to a forward pulse CW. Then, following the time t8, waveforms at the times t1-t8 appear repeatedly and the pulses CW are outputted four times at a cycle of the A phase pulse (or the B phase pulse).
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