| 摘要 |
In cases where the reference signal pulses supplied to one input of the phase detector of a phase-locked loop (PLL) may shift in phase significantly, the PLL may not be able to lock-in quickly enough to the apparent input pulse frequency change. In video monitor circuits where digital counters are clocked by the output frequency of the PLL, for example, the momentary loss of synchronism can cause horizontal scanning of the monitor screen to start too early or too late. A circuit is provided that lets the PLL make normal phase and frequency adjustments during a predetermined period during which counter reset is disabled. The circuit provides a window before and after this period during which counter reset is enabled. A reference pulse with a substantial phase error falls within the window. If three conditions are met, namely, the Reset Enable window exists, the reference pulse occurred within the window and the scan is near the bottom of the monitor screen, then a counter reset to zero signal is produced.
|
