发明名称 ALARMING AND PROCESSING CIRCUIT FOR CODE ERROR RATE DETERIORATION
摘要 PURPOSE:To simplify the scale of circuit constitution by applying multiple processing to accumulated counting of a parity decision bit checking each line quality, corresponding to reception and demodulation of a burst signal sent from plural slave stations, via a count means including prescribed alarm deciding counter and RAM. CONSTITUTION:A parity decision bit 102 is counted in time division at each slave station while being controlled by a timing signal 105 sent from a timing circuit 2 in an error decision counter 4, and stored respectively to a designated address corresponding to each slave station of an RAM 3 while being controlled by a timing signal 104 as a history reference for accumulated count of the parity decision bit in the timing of the next frame. If the accumulated acount of the parity decision bit of a line corresponding to a slave station exceeds a specified threshold value determined in advance, it is decided that the line quality corresponding to the slave station has deterioration and a prescribed code error rate deterioration alarming signal 107 is outputted from the RAM 3.
申请公布号 JPS61224527(A) 申请公布日期 1986.10.06
申请号 JP19850064521 申请日期 1985.03.28
申请人 NEC CORP 发明人 HAMADA TATSUYOSHI;IKEDA NORIYOSHI
分类号 H04J3/00;H04L1/00 主分类号 H04J3/00
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