发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To prevent the erroneous operation of the title device by a method wherein the internal circuit is driven by voltage to be impressed with the breakdown voltage between the drain and source of the FET equal to the minimum channel length in the circuit as the reference. CONSTITUTION:The power source terminal 11 of an internal circuit main body 10 is connected to the output of the voltage transfer circuit consisting of a reference voltage generating circuit 20, an error amplifier 30 and a control element 40; and the potential thereof is nearly equal to the output Vref of the circuit 20. In the circuit 20, an N-type FET 20 is formed equal to the minimum channel length in the main body 10, the drain 25 is connected to a power source 50 through a load 23, the gate is connected to a gate voltage generating circuit 24 and the source is earthed. The potential V2 of the drain 25 becomes nearly equal to the breakdown voltage between the drain and source of the FET and is dropped to Vref by stepping down, the Vref is fed to the error amplifier 30 and V2>Vref C*cc is used as the internal supply voltage. Hereby, the V*cc is constantly held, the erroneous operation of the main body 10, which is caused by the fluctuations of the external power source, is prevented, and moreover, the V*cc can be set in the optimum voltage, whereto the reliability and operating characteristic of the element in the main body 10 are added.
申请公布号 JPS61224347(A) 申请公布日期 1986.10.06
申请号 JP19850063461 申请日期 1985.03.29
申请人 TOSHIBA CORP 发明人 WATANABE YOJI
分类号 H01L27/04;G05F1/46;H01L21/822 主分类号 H01L27/04
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