| 发明名称 |
WIRING PATTERN CONFIGURATION FOR SEMICONDUCTOR DEVICE |
| 摘要 |
PURPOSE:To relax the concentration of stress to the cross parts of the upper and lower wiring patterns and to suppress the generation rate of crack by a method where- CONSTITUTION:A lower wiring pattern Al-I and an upper wiring pattern Al-II, which is provided on the lower wiring pattern Al-I through an interlayer insulating film. |
| 申请公布号 |
JPS61224438(A) |
申请公布日期 |
1986.10.06 |
| 申请号 |
JP19850065646 |
申请日期 |
1985.03.29 |
| 申请人 |
FUJITSU LTD |
发明人 |
INOUE TAKEYUKI;SATO SHINZO;OBA OSAMU |
| 分类号 |
H01L23/522;H01L21/3205;H01L21/768;H01L23/52;(IPC1-7):H01L21/88 |
主分类号 |
H01L23/522 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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