| 摘要 |
PURPOSE:To improve the operating efficiency by inputting an intermittent signal to a base of a transistor (TR) switch via a DC blocking capacitor and a resistance circuit fed with DC bias, turning off the TR switch after a prescribed time decided by a capacitor and a resistor so as to increase the drive current to the load. CONSTITUTION:When the level of a timing pulse tP is logical '1', a clock pulse cP is abnormal a the level '1' continues, an output P of an NAND element 10 goes to level '0' and the capacitor 7 is charged at a voltage division level by resistors 8 and 9. An input point S of an NAND element 11 during that time is shown in the input point S in figure (b). The charging time depends on the C and R and also on the permissible ON duration time of the TR. When the potential of the input point S reaches a prescribed level, the output of the NAND element 11 is inverted from level 1 to level '0' to prevent the ON- duration of a TR 3. Thus, a transformer 6 is used with an effective current and the On-duration of the TRs due to a fault is prevented so as to avoid damages to the TRs. |
