| 摘要 |
PURPOSE:To return a reply signal at high speed to an asynchronous polling by providing the 1st and 2nd buffers and controlling the circuit that the 1st buffer and the 2nd buffer are switched mutually at updating of a status. CONSTITUTION:An address selector 13 selects either an address reading a reply signal or an address written with a new updating status. An address control section 1 generates an address A7(MSB) inputted from a buffer switch control section 10 and addresses A0-A7 formed by incrementing sequentially head addresses A0-A7 decided by addresses A0-A6 inputted from a read control section. The generated addresses A0-A7 are fed to a memory 9 and the reply signal is read on data buses D0-D7 sequentially. The read reply signal is sent to a master station by a transmission section 6.
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