| 摘要 |
PURPOSE:To make a high-speed processing possible by subjecting the peripheral length of each label area of a labeled picture to the pipeline processing with a hard module. CONSTITUTION:The labeling picture is binarized by a ROM 1, and peripheral points are extracted by a logic filter module 2. At this time, a line buffer 3 synchronizes the input picture and the module 2 with each other. A calculating circuit 4 obtains a histogram of label values of the input picture corresponding to outputs of the module 2. This histograms is pipe-joined, and the processing result is transmitted to a higher module 5 in a high speed. This obtained histogram indicates the peripheral length of the pertinent label area.
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