发明名称 ARITHMETIC AND LOGICAL UNIT
摘要 PURPOSE:To execute a data processing at a high speed by generating newly an instruction code by which the number of prescribed codes existing in a data is counted by one instruction. CONSTITUTION:An instruction in an instruction code is constituted of an OP code 20, an operand 21 for storing an address in a memory 12 in which a retrieval data to be checked has been stored, and a variant in which control information of the instruction has been stored. In this state, when this variant 22 is ''0'', the number of bits being ''0'' is counted, and when the variant 22 is ''1'', and ''2'', the number of bits being ''1'', and the number of bits being ''0'' and ''1'' are counted, respectively.
申请公布号 JPS61223940(A) 申请公布日期 1986.10.04
申请号 JP19850063784 申请日期 1985.03.29
申请人 CANON INC 发明人 SUGINO TOSHIO
分类号 G06F7/00;G06F7/76;G06F9/30;G06F9/305 主分类号 G06F7/00
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