| 摘要 |
PURPOSE:To transfer data in a high speed by providing a buffer in a direct memory access DMA controller and controlling asynchronously the system bus side and the auxiliary bus side with handshake logics. CONSTITUTION:In case of data transfer from a memory A to a memory B, a handshake logic A 13 starts the operation by DMA start indication from a CPU 1, and data is transferred from the memory A to the input side of a FIFO buffer 15. After this data reaches the output side of the buffer 15, a hand shake logic B 14 starts the operation. Since many data can be held in the buffer 15, the system bus side is operated in a high speed to release a bus at a proper period, and the CPU 1 is allowed to perform another processing operation during this release period. Thus, the logic A 13 transfers data written in the buffer 15 to the memory B completely to terminate the DMA operation. |
