| 摘要 |
The control unit detects the errors concurrently with normal microinstruction execution through suitable internal checking circuits and a determined microinstruction allocation in the memory. Microinstructions comprise additional field (CS, FS) carrying the encoding, in modified Berger code, of the allocation address of the microinstruction itself and of the following one; the microinstructions of destination itself and of the following one; the microinstructions of destination of conditional jumps are allocated so that their codes are related to each other by simple logic relationships which are then reproduced by an internal circuit (CSM); the two fields, the one of the next microinstruction being duly delayed, are then compared and possible differences detect unidirectional and incorrect sequencing errors. The other errors are detected through particular implementations of some internal circuits (STK1, INC1) and duplication of others (RCT, SEL). |
