| 摘要 |
PURPOSE:To reduce the time necessary for memory refreshing and memory clearing by selectively connecting the refresh clear counter to all the segments, making CAS signals valid simultaneously relative to addresses outputted from a refresh counter and performing a refresh and/or clear operation. CONSTITUTION:During refreshing, CPU refresh commands are fetched by a TR circuit 8, refresh signals are received by a timing generator 2 which outputs RAS signals and a MPX circuit 15 supplies the output of a refresh clear counter 5 as Ref-ADR signal to an address converter 14 and Row address signals are supplied to all of D-RAM segments 7-0 to 7-(2k-1). When the timing generator 2 outputs AD-CONV signals, Column address signals are supplied to AD terminals of all the D-RAM segments 7-0 to 7-(2k-1). DEC circuit 13 simultaneous ly refreshes memory cells designated by Row address signals and Column address signals.
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