| 摘要 |
PURPOSE:To reduce the hardware quantity by making good use of a serial port of a shift register and therefore sharing shift registers of both the transmission reception sides. CONSTITUTION:The transmission data of a data input/output circuit are read to input terminals D0-Dn of a shift register 20. A transmission gate 16 is opened for a prescribed period of time by a transmission pulse Send supplied from a timing circuit 15. Thus the transmission data are sent to a hybrid circuit 18 every bit and synchronously with a clock pulse CLK. In a reception mode of data, a reception gate 17 is opened for a prescribed period of time by a reception pulse Rec. Then the data are supplied successively to a serial port SI of the register 20 from the circuit 18 synchronously with the clock pulse CLK of the circuit 15. When the receiving action rounded by round, the output of the register 20 is fetched to a reception data latch circuit 13 by a load pulse Load via output terminals Q0-Qn. In such a way, the port SI of the register 20 is used effectively and shares the shift registers of both transmission and reception sides are shared. Then the hardware quantity can be reduced. |
