| 摘要 |
PURPOSE:To suppress the yield of parasitic N-P-N bipolar transistor and to prevent erroneous operation such as latch up, fluctuation of the potential of a P well and the like, by forming a low resistance region in the P well and a region, in which the characteristics of an MOS transistor are not affected, and constituting a CMOS-IC. CONSTITUTION:A P-type region 8 is formed in a junction part between a P well and an N-type silicon substrate 1. The N-type region 8 includes boron of about 5X10<18>/cm<-3>, and the concentration of impurities is made higher than the normal value of 1X10<16>/cm<-3> of impurity concentration in the surface of the P well 2 by two orders of magnitude. The low-impurity concentration region in the vicinity of the junction with the N-type silicon substrate, which is the cause of the high surface resistance of the P well, is replaced by the high-impurity concentration region. Therefore, the surface resistance of the P well 2 becomes about 300OMEGA/square. In comparison with the value of about 1 kOMEGA/2.54cm<2> in the conventional structure, said resistance becomes less then one half. Therefore, the gain of the parastic N-P-N bipolar transistor, which is the cause of the yield of latch up, becomes small and the latch up is prevented. The fluctuation of the potential of the P well 2 due to external effect becomes extremely small. |
