| 摘要 |
PURPOSE:To decrease phase difference at switching between a data input signal and a return clock signal by switching a synchronous object input from a reference clock signal into the data input signal after a data input signal pulse comes. CONSTITUTION:A timing generator 6 inputs a switching input signal S8 for the switching control of a switch 1 and a data input signal S2 and after the switching input signal S8 is effective, a frequency division reset signal S9 is generated in response to the pulse of the data input signal S2 incoming at first and sends the result to a frequency divider 5. The frequency divider 5 sends the switching timing signal S10 to the switch 1 so as to switch the signal from the reference clock input signal S1 to the data input signal S2.
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