| 摘要 |
PURPOSE:To shorten the interruption processing time by providing two program counters and two flag registers within a CPU to have changeover between these counters and registers respectively when an interruption is produced and then switching those counters and registers into an original state after the interruption processing routine is executed. CONSTITUTION:An interruption is produced when both the 1st program counter PC1 and the 1st flag register FLAG1 are operated. When a signal INT is active an interruption control part IC delivers a signal INTACK in an interruption enable mode. A changeover circuit KC inverts a signal EN with the signal INTACK and the PC1 and the 2nd flag register FLAG2 are valid. Thus the execution is started for an interruption processing routine shown by the 2nd program counter PC2. When this interruption processing is through, an instruction execution control part IPC delivers a signal IRET to the circuit KC. Receiving this signal IRET, the circuit KC inverts again the signal EN to invalidate both the PC2 and FLAG2 and to validate both the PC1 and FLAG1 respectively.
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