发明名称 TEST SYSTEM OF SYNCHRONOUS TYPE LINE CONTROL CIRCUIT
摘要 PURPOSE:To facilitate a loopback test by synchronizing a signal in a transmission timing sent by a transmission timing sending setting means when a line loopback setting means applies loopback test to a MODEM interface signal of a line control circuit. CONSTITUTION:An interface signal (a) sent from a line interface circuit 9, that is, a transmission data SD, a transmission request signal RS and a transmission synchronizing timing ST1i are reflected by an external connector (b) to apply function test as a reception data RD, a transmission permission signal CS and a reception timing signal RT. The timing signal ST1i is reflected at a terminal TEST for ground of a terminal FG, a level of a setting terminal A of a resistor R is suppressed to OV, an AND circuit 11 sends the timing ST1i to a NOR circuit 13 and the timing ST1i is sent to a terminal ST1 via a NAND circuit 16.
申请公布号 JPS61222346(A) 申请公布日期 1986.10.02
申请号 JP19850055390 申请日期 1985.03.19
申请人 FUJITSU LTD 发明人 ISHIKAWA HIROSHI
分类号 H04L29/14;H04L13/00 主分类号 H04L29/14
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