| 摘要 |
PURPOSE:To make it possible to perform the stable logical operation of a GaAs gate array, which is based on DCFL and has a small logical amplitude, by connecting a plurality of EFETs in parallel, using them as one driver FET, thereby reducing the ON resistance. CONSTITUTION:To a load FET 13 comprising DFET, a first driver FET 11 and a second driver FET 12 are connected in series. The FET 11 on the load side is a single EFET; and the FET 12 on the grounding side is constituted by connecting two EFETs 121 and 122 in parallel. The FET 11, the FET 121 and the FET 122 are prepared in one basic cell and have the same size. Therefore, the ON resistance of the FET 12 on the grounding side becomes low. As the noise margin on the low level side of an input A, about 0.2V can be secured. Thus, a NAND gate, which can be operated sufficiently stably, can be implemented.
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