| 摘要 |
A multi-input logic circuit comprises a multi-emitter transistor having emitters which are connected to a logic input terminals of the multi-input logic circuit, a PNP type transistor having a base which is connected to a collector of said multi-emitter transistor and a level shift element which is connected to an emitter of the PNP type transistor. This arrangement facilitates the maintenance of an improved margin of threshold voltage to input voltage. |
