| 摘要 |
PURPOSE:To shorten access time and to stabilize reading operation by using a MOSFET for precharging in time division as active load having high resis tance. CONSTITUTION:In a non-equalizing period, the clock -phiE1 of large amplitude becomes 'H', and the gate voltage of the MOSFET for equalizing 56 rises to power source voltage VDD and becomes off, and connection to bit lines 22 and 23 is released. In non-precharging period, which is the same timing with the non-equalizing period, -phiE2 of small amplitude becomes 'H', and gate volt age of MOSFET 54 and 55 for precharging rises and FET 54 and 55 are biased to the state near the saturation area and becomes constant current load, and its equivalent resistance becomes fairly high. Accordingly, data signal voltage that falls and rises steeply is generated in lines 22 and 23 by current IB, -IB that flows into the cell 10, and thereby access time can be shortened. Thus, FET 54, 55 perform precharging operation and active loading operation in time division. |
