| 摘要 |
PURPOSE:To change optionally pulse width by giving respectively the output of the 1st and 2nd delay circuit to each input of the 1st and 2nd logic circuit. CONSTITUTION:The 1st and 2nd delay circuit 10A, 10B apply two pairs of pulse signals having a timewise deviation to the 1st and 2nd logic circuits 1A, 1B while retarding at every one pair of two pairs of input pulse signals in the relation of in-phase or complementary phase. Both the logic circuits 1A, 1B output a pulse only when both the inputs are at the 1st and 2nd level at the same time. In such a case, the delay circuits change the overlapped time in matching with the condition between the pulse signal pair so as to control freely the pulse width of each output pulse signal.
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