| 摘要 |
<p>A 12 bit, 10 megahertz subranging analog-to-digital converter feeds a sampled analog input signal forward, without delay or attenuation, to a summing node. The sampled analog signal is converted by an MSB flash encoder to a 7 bit MSB word that is converted to an analog signal by a 7 bit DAC having 14 bit accuracy. The result is subtracted from the sampled analog signal to produce a residue signal. A MOSFET isolation switch coupled between the summing node and the input of a high speed amplifier isolates the amplifier until the residue signal is stable, to prevent overdriving of the amplifier. A positive error voltage is added to the reference voltage inputs of the MSB flash encoder to enable use of a digital error correcting circuit that does not need to operate on negative binary numbers. A novel sample and hold circuit includes a closed loop operational amplifier that isolates the sampling capacitor and provides low output impedance to drive the MSB flash encoder and the summing node, provides low, stable, input offset voltage and very high bandwidth. The operational amplifier includes N-channel FET source followers coupled by balanced bias and level shifting circuitry to an NPN differential amplifer stage. Symmetrical, buffered cross-coupling form each of the source follower FETs to the opposite level shifting circuitry increases the amplification thereof and results in low DC offset voltage, high input impedance, and high gain and bandwidth.</p> |
