| 摘要 |
PURPOSE:To obtain a discrimination circuit which can make amplitude regeneration and retiming of received signals with a simple constitution, by providing a slicer, AND circuit, and NRZ-encoding circuit. CONSTITUTION:Since the input 6 of a discrimination circuit is a received signal, it has a waveform with a disturbed amplitude and phase as shown in figure (a). Since a slicer 1 amplifies and amplitude-limits the input 6 of the discrimination circuit, the output 7 of the slicer 1 still contains a phase jitter as shown in the figure (b). A clock 8 has the same frequency as the transmitting speed of the received signal and the phase relation between the clock 8 and slicer output 7 is such one that the clock 8 becomes logic '1' when the slicer output 7 is a fixed value as shown in figures (b) and (c). Therefore, the output 9 of an NRZ/RZ converting section 2 becomes a signal of RZ code containing no phase jitter as shown in figure (d). Since a delaying section 3 delays the output 9 by a time equal to the 1/2 of the cycle of the clock 8, the output 10 of the delaying section 3 is delayed by the time equal to the 1/2 of the cycle of the clock 8 as shown in figures (d) and (e). Since an OR gate 4 takes the OR of the outputs 9 and 10 and causes the OR to become a discriminator output 11, the output 11 has a waveform, to which amplitude regeneration and retiming are performed and which are free from noises and phase jitters, as shown in figure (f).
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