| 摘要 |
PURPOSE:To increase a bit line signal voltage and to make possible fast reading by disposing a sense circuit at both sides of a cellarray at two times pitch as large as a pitch in the direction of the word line of a memory cell, multi- dividing the bit line and transmitting them to the sense circuit at both the sides by using a main bit line which is not directly connected to the memory cell. CONSTITUTION:When a certain word line of a left side in a sub-block 1-2 is selected, a memory cell information activated, by the word line is read on bit lines 2-1, 2-3. On bit lines 2-2, 2-4, a dummy cell information activated by a dummy word line 7 is read at the same time of the memory cell information. The memory cell information and the dummy cell information (reference signal) on the bit lines 2-1, 2-2 in the sub-block 1-2 are inputted to a sense circuit 9-1. The memory cell information and the dummy cell information (reference memory cell information and the dummy cell information (reference signal) on the bit lines 2-3, 2-4 in the sub-block 1-2 are inputted to a sense circuit 9-2. By both the sense circuits, the signals are amplified and two memory cell informations are externally read. |
