| 摘要 |
PURPOSE:To transmit data of plural bits in high speed without causing synchronizing deviation by obtaining a synchronous signal at a code midpoint having a longer code period and transmitting the data of plural bits by means of the NRZ system in the lump at coincidence of one address while applying intermediate correction of a clock for data transmission/reception. CONSTITUTION:When a code string pattern latched by a latch 65 of a code string pattern detection section 59 is coincident with an address stored in an address memory section 87a in a parallel/serial converter 85, which inputs a 16-bit or 8-bit data of an output data memory section 87b stored at a location corresponding to the address storage section and the data is outputted serially to a data transmission line 5 sequentially via a transmission gate 79 and a main gate 77 synchronously with a data transmission/reception signal Dc. In this case, a pause part is provided at the middle position on the way of an area of the code 1, the synchronization is taken again at the midpoint with respect to a 16-bit data, a clock 55 is corrected and the 8-bit data transmission/ reception signal is outputted in the NRZ code twice.
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