发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To make possible high speed operation and low power consumption by controlling the second transmitting gate MOSFET for transmitting plural selecting timing signals to the gate of a switch MOSFET, and providing a precharge MOSFET to each gate of the second transmitting gate MOSFET, respectively. CONSTITUTION:An output signal of a NOR gate circuit is transmitted to each gate of transmitting gate MOSFETQ22-Q25 respectively through transmitting gates MOSFETQ14-Q17. To these gates of the transmitting gate MOSFETQ14-Q17, converted line selecting timing signals phit00-phit11 are respectively supplied. Between the respective gates of the transmitting gates MOSFETQ22-Q25 for transmitting word line selecting timing signals phix00-phix11 to respective word lines W0-W3 and a power source voltage Vcc, precharge MOSFETQ18-Q21 are respectively provided.
申请公布号 JPS61217989(A) 申请公布日期 1986.09.27
申请号 JP19850058362 申请日期 1985.03.25
申请人 HITACHI LTD 发明人 YANAGISAWA KAZUMASA;ONO KUNIO
分类号 G11C11/408;G11C11/34 主分类号 G11C11/408
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