| 摘要 |
PURPOSE:To enable accurate measurement of phase difference value at a desired accuracy, by forming a third signal with the frequency of F=fn/(n-1) [wherein (n) is measuring accuracy and fi frequency) of F to sample one of two signals at the rising or falling of the third signal. CONSTITUTION:Two signals f1 and f2 shall be the same in the frequency. The signal f1 is inputted into a D input terminal of an FF1 while the signal f2 is divided 2 in 1/n to form a synchronous pulse with a one-shot multivibrator circuit 3 and the synchronous pulse generated within the (1/n)f2 is supplied to an nf2/(n-1) generator 4 and a 1/n divider 5. Then, the signal of nf2/(n-1)=F1 generated 4 is counted 5. The signal of F1 is inputted into a clock terminal C of the FF1 and the Q output is introduced to an (m) bit latch circuit 6 as latch signal. Receiving this latch signal, the circuit 6 latches counts by counting 5 as (m) bit output to sent the data latched to a CPU as phase difference.
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