| 摘要 |
PURPOSE:To avoid the competition for buses by dividing a bus cycle into plural time slots and controlling the buses with allocation of time slots. CONSTITUTION:A bus master 22 divides the cycle of a system bus 21 into four time slots #0-#3 and delivers the corresponding time slots number to the bus 21. A microprocessor 23 is connected with modules 20-1-20-4 via a control bus 24 and also with the master 22 via a signal line 25 for synchronization. Either one of these modules contains a transmission station Si, a reception station Ri and registers STARi, RTARi and STSRi respectively. The registers STARi and RTARi designate time slots Si and Ri respectively. While the register STSRi shows the status of the module 20-i. |
