| 摘要 |
PURPOSE:To realize two types of writing operation modes and to improve a mass productivity and memory function by identifying a change timing of a write enable signal, and controlling an operation of a data output buffer in referring to a change timing of a column address strobe signal. CONSTITUTION:An internal complementary address signal in accordance with address signals AY0-AYn supplied through an external terminal is formed, and similarly transmitted to a column decoder C-DCR constituted by a static type circuit. The column decoder C-DCR decodes a transmitted address signal and selects a data line by a data line selecting timing signal phiy. A timing control circuit TC receives a low address strobe signal RAS supplied through the external terminal, a column address strobe signal CAS and a write enable signal WE and forms respective types of internal timing signals. Wherein, in order to obtain a variety of an output function of a RAM, in the timing control circuit TC, a timing identifying and controlling circuit is provided.
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