发明名称 INTERRUPTION CONTROL SYSTEM
摘要 PURPOSE:To prevent an overlapping with other definition data by providing a means for detecting a change of a condition of the interruption generation, and transmitting a previously defined and corresponding interruption data even when the generated interruption cause is removed on the way. CONSTITUTION:In an interruption data register 7, an FF7 is provided in addition. When an output data from the register 7 is 1001, a data showing the interrupting cause is removed on the way is previously defined. When the interrupting cause (a) out of the interrupting causes (a)-(d) is produced, an interruption signals is turned on in a logical OR section 3. Thereby, a microprocessor MPU 1 turns on and off twice an interruption response signal at a prescribed interval and transmits to the data register 7. In this case, even when, the cause (a) is removed on the way, the previously defined data 1001 as the output data of the register 7 is transmitted to the MPU 1, thereby the MPU receives it as an interruption withdrawal data and carries out a processing thereafter. Thereby, an overlapping with other definition data can be prevented.
申请公布号 JPS61216072(A) 申请公布日期 1986.09.25
申请号 JP19850031763 申请日期 1985.02.20
申请人 FUJITSU LTD 发明人 SATO SHINICHI
分类号 G06F13/24;G06F9/46;G06F9/48 主分类号 G06F13/24
代理机构 代理人
主权项
地址