| 摘要 |
PURPOSE:To attain writing on a memory despite the increase in the number of address signals to be transmitted by transmitting parallel address signals after converting them into a serial signal. CONSTITUTION:The parallel address signals 2, 2', 2''... are converted successively into a serial address signal 14 by a clock signal 15 through a converting circuit 13. This signal 14 is sent to a device 5 via a transmission line 21 and used as a serial address signal 17 for input. While a reset signal 16 delivered during variation of the signals 2, 2'. 2''... is supplied to the device 5 via a transmission line 23 as a reset signal 19. A clock signal 15 is sent to the device 5 via a transmission line 22 as a clock signal 18. Then a write signal 4 which indicates the data writing timing to a memory is supplied to the device 5 via a transmission line 12 as a write signal 9.
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