| 摘要 |
PURPOSE:To speed up quadruple-precision division by using efficiently a double- precision divider, a double-precision multiplier, and a quadruple-precision precision adder subtracter that a computer system is equipped with. CONSTITUTION:A divisor is set in a divisor register DSR 1 firstly and a dividend is set in a dividend register DNR 2. When division is carried out, the double- precision divider DDR 6 calculates an approximate value of the mantissa part of the high-order double-precision part of a quotient generated in quadruple- precision division, and the multiplier MXD 7 which calculates the product of a multiplier and a multiplicand and the quadruple-precision adder subtractor AXR 8 calculates the real value X of the quotient and partial residue (p) at the same time. When the residue (p) is not zero, the divider DDR 6 calculates an approximate value Y' of the mantissa part of the low-order double-precision part of the quotient of the quadruple-precision division and the multiplier MXD 7 and adder subtracter AZR 8 calcualte the read value Y of the mantissa part of the low-order double-precision part and the real residue py. |
