| 摘要 |
PURPOSE:To improve the profitability of a DRAM control circuit by using a DRAM control LSI of a smaller size with only a pair of normal access requests and then combining said LSIs with two pairs of normal access requests respectively. CONSTITUTION:When a refresh request signal RFR Q1 is supplied to an LSI1-1 at one side from the outside, a conflict occurs between the RFR Q1 and a normal access request signal AS 1. Then a refresh action is started and a ready signal RDY 1 is set at 'L' (low) as long as no signal AS 1 is available. Then a refresh request is given to an LSI1-2 by a refresh request signal RFR Q2 of the LSI1-2. Then a refresh action is started if no normal access request signal AS2 is given from an access requester at the other side. When the signal AS 1 or AS 2 given from a normal access requester is available, both ready signals RDY 1 and RDY 2 are set at 'L' respectively after the conflict occurred between access request signals AS 1 and AS 2 and refresh request signals RFR Q1 and RFR Q2 respectively.
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