| 摘要 |
PURPOSE:To change easily the period of a clock signal by constituting a timing signal generator with a counter, a PLA circuit, and a clock signal generator. CONSTITUTION:A timing signal generating circuit 101 consists of a counter 102, a PLA circuit 103, and a clock signal generator 104. When a start signal Vs is applied, the PLA circuit 103 outputs a reset signal to the reset terminal R of the counter 102. Then, the counted value of the counter 102 is reset. The counter 102 starts counting system clocks from the generator 104 and inputs the counted value to the PLA circuit 103. The PLA circuit 103 outputs a timing signal CP having a period programmed preliminarily in accordance with the bit state of the input signal. Thus, the period of the clock signal is changed easily.
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